This invention relates to a structure and method which insure correct alignment of a large number of closely spaced solder bumps which extend between two facing planar surfaces. A need for the invention exists in numerous modern electronic systems.
An example of an electronic system to which this invention is relevant is the module of stacked integrated circuit (IC) chips developed by the assignee of this application for use with focal plane detector arrays, as shown in U.S. Pat. No. 4,551,629 and 4,672,737. A two-dimensional focal plane array of photodetectors may contain thousands of separate photodetectors, each electrically connected to a separate lead (having a terminal) at the focal plane surface of a module compromising a large number of stacked layers, each of which layers is an integrated circuit (IC) chip. The photodetector signals are separately amplified and filtered in the module, prior to multiplexing the parallel signals and transmitting them from a back plane surface of the module to remote circuitry. An example of a focal plane configuration is one having 64.times.64 detectors in the array, i.e., a total of over 4,000 detectors. Center-to-center spacing between detectors, and between their respective terminals on the module, is presently as low as 4 mils (0.004 in.), and may eventually be pushed as low as 2 mils (0.002 in.).
Clearly, the problem of providing a separate solder connection between each photodetector and its terminal on the module is extremely difficult. The term "solder" is used to mean any electrically conductive material which extends between each detector and its terminal. Solder bumps may be used in "flip-chip" bonding, i.e., a process in which solder bumps formed on facing planar surfaces are aligned, and then brought together to provide the desired individual, parallel electrical connections. Such a bonding process is discussed in common assignee U.S. Pat. No. 4,912,545.
Another example of an electronic system to which this invention is relevant is disclosed in common assignee U.S. Pat. No. 4,706,166. That patent relates to a practical method of forming an electronic memory module comprising stacked IC chips. The stacked module has a multiplicity of terminals formed on its access plane. Matching terminals are provided on a substrate having electrical lead-out conductors thereon. Aligned bonding (solder) bumps are formed on both the module terminals and the substrate terminals. After careful microscopic alignment, the two groups of solder bumps are moved together and flip-chip bonded. The solder is preferably reflowed by heating, in order to form welded joints. However, if heating threatens any part of the structure, pressure alone may be relied on to join the aligned solder bumps.
The shortest center-to-center distances between solder bumps on the memory module and its substrate will usually be 10 mils (0.010 in.). So the alignment task is not as daunting as in the photodetector bonding. But it is still a significant problem.
Flip-chip bonding is a recognized method of connecting aligned terminals located on facing planar surfaces. Flip-chip aligner bonders are available as manufacturing apparatus. Such bonders use suitable alignment techniques, such as optical alignment using radiation wavelengths to which one of the planar surfaces is transparent. Flip-chip aligner bonders also require leveling systems which can insure exact parallelism of the facing planar surfaces.
In other words, there are two problems which can interfere with the success of flip-chip bonding. Bonding failure can occur (1) from misalignment of matched bumps, or (2) from variations in the height of bumps sufficient to prevent their engagement even if aligned. The latter problem is often referred to as the planarity problem, because variations of the planar surfaces which support the bumps may prevent two matched bumps from engaging one another. If the opposing surfaces are not exactly parallel, or if one or both surfaces are not exactly flat, such failure of bump engagement may occur.
The present invention deals with these problems by providing a solder bump alignment process which, in effect, replaces flip-chip bonding techniques in aligning simultaneously many bonds having minimal center-to-center spacing.
A prior art process used to provide an improved version of flip chip bonding is an IBM process referred to as C4 (controlled collapse chip connection). A recent IBM patent, U.S. Pat. No. 5,075,965, summarizes the process: "In the C4 process, as distinguished from the earlier flip chip process, the solder wettable terminals on the chip are surrounded by ball limiting metallurgy, and the matching footprint of solder wettable terminals on the card are surrounded by glass dams or stop-offs, which are referred to as top surface metallurgy. These structures act to limit the flow of molten solder during reflow." (Column 2, lines 39-46). "To be noted is that the C4 process is a substantially self-aligning process. This is because of the interaction of the geometry of the solder columns or balls prior to reflow with the surface tension of the molten solder during reflow and geometry of the solder columns. When mating surfaces of solder column on the chip and the conductive footprint contact on the card touch, the surface tension of the molten solder will result in self alignment." (Column 3, lines 36-44).
The present invention provides a process which insures solder bump-to-terminal alignment. It has major advantages over the C4 process in certain situations. One such situation is where very small dimensions are required in center-to-center spacing of solder bumps. Another is the situation where a plurality of surface-to-surface bondings are required in a single package, i.e., a package in which transparent layers are not available for alignment purposes. A third advantage of the present invention over the C4 process is that it can be performed at lower temperatures, thus avoiding damage to nearby temperature sensitive elements, e.g., photodetectors.